Power MOSFETs (metal oxide field effect transistors) are well known in the semiconductor industry. Two types of known power MOSFET cell structures are shown in FIGS. 1 and 2. FIG. 1 is a cross section view of a conventional vertically-conducting UMOS structure, and FIG. 2 is a cross section view of a power MOSFET with source trenches and planar gate structure.
In FIG. 1, gates 110a,b are formed in gate trenches 113a,b extending from the top surface through body region 106, and terminating in n-type epitaxial region 104. Vertical channels are formed between source regions 114a,b and epitaxial region 104 along the sidewalls of gate trenches 113a,b. Although this structure has a relatively low on-resistance and enables high packing density due the vertical gate structure, it suffers from high input capacitance (i.e., high gate to source and gate to drain capacitance) due to the long channel length and the large number of gates of a highly packed device.
In FIG. 2, a conventional double-diffused MOS (DMOS) planar surface structure is combined with source trenches 213a,b. Source trenches 213a,b extend from the top surface into epitaxial region 204, and are filled with conductive material 216a,b (e.g., polysilicon). Conductive material 216a,b are insulated from epitaxial region 204 and body regions 206a,b by a layer of insulating material 212a,b, but are electrically connected to the body/source regions through the top metal layer 218. A maximum forward blocking voltage, hereinafter referred to as xe2x80x9cthe breakdown voltagexe2x80x9d, is determined by the avalanche breakdown voltage of the reverse-biased body-drain junction. Source trenches 213,b help achieve a higher breakdown voltage by causing the electric field to spread deeper into epitaxial region 204. This structure however suffers from the same horizontal limitations (e.g., packing density and JFET resistance) as conventional planar DMOS structures.
Thus, there is a need for a power MOSFET structure which, among other advantages and features, exhibits low input capacitance, high breakdown voltage, improved packing density, and low on-resistance.
In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region of a first conductivity type, a gate trench which extends into the first semiconductor region, and a source trench which extends into the first semiconductor region. The source trench is laterally spaced from the gate trench.
In one embodiment, the source trench extends deeper into the first semiconductor region than the gate trench.
In another embodiment, the MOSFET further includes a body region and a source region. The body region is in the first semiconductor region between the source trench and the gate trench. The body region is of opposite conductivity type as the first semiconductor region. The source region is in the body region such that a channel is formed in the body region along a sidewall of the gate trench. The source region is of the same conductivity type as the first semiconductor region.
In accordance with another embodiment of the present invention, a method of forming a MOSFET is as follows. A first semiconductor region of a first conductivity type is formed. A gate trench extending into the first semiconductor region is formed. A source trench extending into the first semiconductor region is formed. The source trench is laterally spaced from the gate trench.
In one embodiment, a body region is formed in the first semiconductor region between the source trench and the gate trench. The body region is of opposite conductivity type as the first semiconductor region. A source region is formed in the body region such that a channel is formed in the body region along a sidewall of the gate trench. The source region is of the same conductivity type as the first semiconductor region.